Transistors are generally formed on the top surface of a semiconductor substrate. Typically, the semiconductor substrate is divided into a number of active and isolation regions through an isolation process, such as field oxidation or shallow trench isolation. A thin oxide is grown on an upper surface of the semiconductor substrate in the active regions. The thin oxide serves as the gate oxide for subsequently formed transistors.
Polysilicon gate conductors are formed in the active regions above the thin oxide. The gate conductor and thin oxide form a gate structure which traverses each active region, effectively dividing the active region into two regions referred to as a source region and a drain region. After formation of the polysilicon gates, an implant is performed to introduce an impurity distribution into the source/drain regions. Generally, source/drain regions are heavily doped with n-type or p-type dopants.
Transistor manufacturers continually work to decrease transistor size. Smaller transistors, of course, require smaller transistor component dimensions. As the critical transistor dimensions continue to decrease, the thickness of the gate oxide also needs to be reduced. Nevertheless, a major drawback to the decreased gate oxide thickness (e.g., &lt;30 .ANG.) is that direct tunneling leakage current increases as gate oxide thickness is decreased. To suppress gate leakage current, material with a high dielectric constant (k) can be used as a gate dielectric instead of the conventional gate oxides, such as thermally grown silicon dioxide.
High-k gate dielectric materials have advantages over conventional gate oxides. A high-k gate dielectric material with the same effective electrical thickness (same capacitive effect) as a thermal oxide is much thicker physically than the conventional oxide. Being thicker physically, the high-k dielectric gate insulator has less direct tunnel leakage current. Tunnel leakage current is exponentially proportional to the gate dielectric thickness. Thus, using a high-k dielectric gate insulator significantly reduces the direct tunneling current flow through the gate insulator.
High-k materials include, for example, aluminum oxide (Al.sub.2 O.sub.3), titanium oxide (TiO.sub.2), and tantalum pentaoxide (TaO.sub.5). Al.sub.2 O.sub.3 has a dielectric constant (k) equal to eight (8) and is relatively easy to make as a gate insulator for a very small transistor. Small transistors often have a gate physical length less than 80 nm.
Despite its advantages, high-k materials pose IC fabrication challenges. For example, high-k material is relatively difficult to etch, unlike conventional thermal oxide. Residual material associated with chemical etchants for high-k materials can contaminate the IC wafer. As such, a new etching recipe, or method, needs to be developed for different high-k materials. Furthermore, high-k material is usually deposited or sputtered onto the silicon wafer. Deposition or sputtering results in an unsatisfactory uniformity of thickness across the wafer.
Thus, there is a need for a method of forming a high-k dielectric gate insulator in MOS transistors that does not use chemical etching processes. Further, there is a need for a method of forming a high-k dielectric gate insulator with a satisfactory uniform thickness. Even further, there is a need for the formation of a high-k insulator which is self-aligned to the gate area of both n- and p-channel transistors.